Teo Swee Ann of Espressif confirms a default shift to RISC-V, "unless we have certain special needs."
Tensilica is being phased out in favour of components developed on a free and open source instruction set architecture.
Teo Swee Ann, Espressif's CEO and President, has announced that the business would focus solely on parts based on the free and open source RISC-V instruction set architecture, signalling the end of an era for the company's successful Tensilica-based line.
Espressif is well known for developing the ESP8266 and ESP32 embedded systems-on-chip family (SoCs). The bulk of the chips are designed on Tensilica microcontroller cores - the Tensilica Diamond in the ESP8266 and the Tensilica Xtensa in the ESP32 - and may be found in everything from hobbyist development boards to commercial goods.
However, the business has recently began to produce ESP32 components with cores based on the free and open source RISC-V instruction set architecture. RISC-V cores were first introduced as coprocessors alongside one or more principal Tensilica cores; however, the firm has recently disclosed an increasing number of components that are solely RISC-V, including the ESP32-C3 and the recently released footprint-reduced ESP32-C2.
Espressif chief executive and president Teo Swee Ann made it plain on LinkedIn in response to a question about whether the firm was going to RISC-V exclusivity: RISC-V is the way ahead for the company. Teo writes, "Yes, that is true," about the company's migration to RISC-V. "Unless we have some unique requirements for anything else that I'm not aware of right now."
Teo's blog post about the ESP32-C2, which is now sampling, is a good place to start learning more about it.